Dates:
July 29 - 30, 2020
9:00 am - 12:30 pm PDT on both days
All sessions held by Zoom. (The poster session held by Gather.town .)
Agenda:
Wednesday, July 29
9:00-9:15
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Introduction
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Mark Horowitz
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9:15-10:00
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Keynote Talk:
The End of Four Ages of Computer Architecture and the New Fifth Age
[video]
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John Hennessy
|
10:00-10:15
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An AHA Perspective
[pdf] [video]
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Priyanka Raina
|
10:15-10:45
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Deep Dive Talk 1:
Connecting Polyhedral Optimization to CGRA Buffer Generation
[pdf] [video]
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Qiaoyi (Joey) Liu
Dillon Huff
Jeff Setter
|
10:45-11:15
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Deep Dive Talk 2:
A General Mapping Flow in an Agile Hardware World
[pdf] [video]
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Ross Daly
Caleb Donovick
|
11:15-11:45
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Lightning Talks for Posters: (See videos)
-
clockwork: A Polyhedral Compiler for High Throughput, Low Latency
Image Processing Accelerators (Dillon Huff)
-
Creating a Cost Function for Optimizing Loop Fusion in Clockwork
(Isabela Barros David Rodrigues)
-
Aetherling: Type-Directed Scheduling of Streaming Accelerators
(David Durst)
-
Magma and Fault: Python Embedded Hardware Construction and
Verification Languages Designed for Productivity, Performance, and
Correctness (Lenny Truong)
-
Gemstone: A Framework for Flexible and Reusable Hardware
Generators (Raj Setaluri)
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Improved FSM Verification for Generator Frameworks (Keyi Zhang)
-
Source-Level Debugging for Generator Frameworks (Keyi Zhang)
-
mflowgen: A Modular Flow Generator for Enabling Agile Principles in
Physical Design (Chris Torng)
-
Garnet CGRA SoC Architecture and Physical Design (Alex Carsello &
James Thomas)
-
Hardware Support for a Flexible Memory System and Dynamic Partial
Reconfiguration (Taeyoung Kong)
-
Optimizing PE Tile Energy and Delay (Kathleen Feng)
-
Improving Energy Efficiency for DNNs with Temporal Scheduling in
the PEs (Ankita Nayak)
-
Improving Energy Efficiency for CGRAs with Low-Overhead
Fine-Grained Power Domains (Ankita Nayak)
-
Demo: Generating Garnet and Running Test Applications
(Teguh Hofstee)
-
Creating a Cost Function for Auto-Scheduling Applications on the
Garnet SoC (Kalhan Koul)
-
Running Accelerated Halide Programs End-to-End on an SoC
(Charles Tsao)
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FPGA Emulation of Mixed-Signal Systems (Steven Herbst)
|
|
11:45-12:30
|
Poster Session (in Gather.Town)
|
All
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Thursday, July 30
9:00-9:30
|
Deep Dive Talk 3:
Formal Checkers and Solvers for Hardware Design and Verification
[pdf-Mann] [pdf-Niemetz] [video]
|
Makai Mann
Aina Niemetz
|
9:30-10:00
|
Deep Dive Talk 4:
Lake Memory Generator and SMT for Automated Memory
Configuration
[pdf] [video]
|
Max Strange
Kavya Sreedhar
Nestan Tsiskaridze
|
10:00-10:30
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Discussion, Break (in Gather.Town)
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All
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10:30-11:00
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Deep Dive Talk 5:
Design Space Exploration of Processing Element Architectures
[pdf] [video]
|
Jack Melchert
Kathleen Feng
|
11:00-11:45
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Industry Spotlight (Speaker bio):
-
Dr. Shoaib Kamil, Principal Scientist, Creative Intelligence Lab,
Adobe Research
-
Dr. Brucek Khailany, Director of VLSI Research, NVIDIA
-
Dr. Drew Wingard, Director of Silicon Methodology, Facebook
-
Nafea Bshara, VP/Distinguished Engineer, Amazon Web Services
|
|
11:45-12:00
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Closing Thoughts
[video]
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Pat Hanrahan
|
12:00-12:30
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Open Discussion with Industry Speakers, Faculty & Students
(in Gather.Town)
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All
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